The invention generally relates to implantable medical devices and in particular to error detection and correction techniques for use within such devices.
A wide variety of implantable medical devices are provided for surgical implantation into humans or animals. One common example is the cardiac pacemaker. Another is the implantable cardioverter defibrillator (ICD). State of the art implantable medical devices often include a programmable microcontroller for controlling the functions of the device to detect medical conditions within the patient in which the device is implanted and to control delivery of appropriate therapy. Within a pacemaker, for example, the microcontroller monitors the detection of P-waves and R-waves within electrical heart signals to determine whether an episode of bradycardia has occurred and, if so, controls a pulse generator to generate pacing pulses for delivery to the heart. Within an ICD, for example, the microcontroller analyzes P-waves, R-waves and other electrical signals of the heart to determine if an episode of ventricular fibrillation has occurred and, if so, controls a shocking circuit to generate a defibrillation shock for delivery to the heart. In addition to performing functions directed to deliver of therapy, the microcontroller coordinates all other functions of the implantable device such as: monitoring a battery of the device to determine if the battery needs to be replaced; switching of the mode of operation of the device from, for example, a single-chambered pacing mode to a dual-chambered pacing mode; and recording events such as detection of P-waves and R-waves for diagnostic purposes.
The microcontroller operates using control software and data stored in a memory system of the implantable device. The control software specifies the operations to be performed by the microcontroller. The control data provides parameters for controlling the software, such as parameters specifying the amount of electrical energy to employ for pacing pulses or defibrillation shocks or specifying whether the device is to operate in a dual-chamber or a single-chamber mode. The memory system also stores diagnostic information for subsequent transmission to an external programmer device for review by physicians or other personnel. The diagnostic information may include patient diagnostic data such as digitized recordings of internal electrogram (IEGM) signals and device diagnostic data such as measured battery voltages, lead impedances, and the like. Data stored in the memory system, including the control software, is stored in binary form, i.e. the data is stored as sequences of bits comprising ones or zeros. State of the art devices have memory systems storing one megabyte or more of binary data wherein a byte comprises eight bits of binary data.
Significant problems can arise if an error occurs in the control software or other data stored within the memory system. Errors can occur, for example, as a result of alpha particles striking the memory or as a result of atmospheric neutron flux, either of which can cause one or more of the individual binary values stored in the memory system to flip from a one to zero or vice versa. If the error occurs in the portion of the memory storing control software, the microcontroller might no longer be able to operate correctly and, as a result, might administer therapy when none is required or fail to administer therapy when it is required. In some cases, an error in the control software might prevent the microcontroller from operating at all, resulting in a complete lack of therapy. If the error occurs in the portion of the memory storing the control parameters, the microcontroller will likely continue to operate but might implement an incorrect mode of operation (such as performing single-chamber pacing instead of dual-chamber pacing) or might apply too much or too little electrical energy in pacing or defibrillation pulses. Errors occurring in the portion of the memory storing diagnostic information can result in a subsequent misdiagnosis of medical conditions within the patient by a physician reviewing the data or can result in a failure to properly determine when batteries or leads of the implanted device need to be replaced.
As can be appreciated, there is a significant need to provide reliable error detection and correction techniques for automatically detecting and correcting errors occurring within the memory system to ensure that the microcontroller performs the correct functions using the correct control parameters and stores the correct diagnostic data. Preferably, errors are detected and corrected promptly to ensure that the errors do not affect the delivery of therapy. Ideally, an error detection and correction system is provided that can examine data as it is read from memory to immediately detect and correct any errors found therein such that the microcontroller is never at risk of receiving erroneous data. Also, ideally, the error detection and correction system is capable of detecting and correcting either single bit or multiple bit errors. However, to achieve immediate detection and correction of single- or multiple-bit errors, the error detection and correction system typically needs to be implemented entirely in hardware to ensure quick operation and typically must devote a large percentage of the total memory space to error detection and correction bits. To this end, an error detection and correction system could be provided employing five error detection and correction bits for each eight-bit byte of actual data. By providing five error detection and correction bits per byte, single or multiple-bit errors can be detected and corrected using hardware as the data is read. However, the error detection and correction overhead necessitated by such as system is 62.5% (i.e. 13 total bits per byte/8 data bits per byte*100). In other words, fully 38.5% of the memory of the implantable device is devoted to error detection and correction bits and only 61.5% of the memory actually stores useable data, such as control software, control parameters, or diagnostic data. The many error detection and correction bits consume considerable circuit space within the implantable device and consume considerable power and thereby significantly and adversely affect the size, cost and longevity of the implantable device. Moreover, to provide the error detection and correction just described, the device would need to be designed and manufactured using thirteen-bit memory chips. Hence, implantable devices that have already been implanted cannot easily be upgraded to provide error detection and correction. For at least these reasons, error detection and correction systems of the type described are typically not implemented within implantable medical devices. Instead, some implantable devices perform only error detection, but no correction, or perform no error detection or correction whatsoever.
Accordingly, it would be highly desirable to provide an improved error detection and correction system for use within an implantable medical device, which achieves an adequate degree of error detection and correction with minimal overhead to thereby reduce the amount of memory space required to implement error detection and correction and to also reduce the amount of power consumed. It would also be highly desirable to provide an embodiment of the improved error detection and correction system that can be implemented entirely in software so that medical devices that have already been implanted can be upgraded to provide error detection and correction merely by loading new software into the device. It is to these ends that aspects of the invention are primarily directed.
In accordance with a first aspect of the invention, a hybrid hardware/software error detection and correction system is provided for performing error detection and correction within an implantable medical device. The implantable device includes a microcontroller for controlling operations of the device and a memory unit for storing control software and data for use by the microcontroller. The error detection and correction system includes a hardware-based error detection unit for performing a parity check on a row of the memory and a software-based single-bit error correction unit, responsive to the detection of a parity error in a row of the memory, for correcting a single bit error within the row.
In an exemplary embodiment of the first aspect of the invention the implantable device is a cardiac stimulation device for administering pacing therapy. The memory employs nine-bit random access memory (RAM) chips having a parity bit hardwired to each data-storage byte. Each byte represents one row of the memory. The error detection unit comprises hardwired circuitry within the memory chip for performing a parity check on each byte of data as the byte is read during a read cycle. Hence, single bit upset errors are detected immediately upon reading a byte containing an error. The error correction unit is implemented as a software module for correcting single bit errors using a set of column parity bits and a page parity bit, which are calculated and stored by the error correction unit in memory. By providing error detection in hardware and error correction in software, single bit errors can be immediately detected during read operations such that the microcontroller is not at risk of receiving data with single bit errors. Yet the total error detection and correction overhead is kept low so that the size, cost, and longevity of the implantable device are not significantly and adversely affected. For a 32 K-byte memory chip, the total parity bit overhead is only 13.28%xe2x80x94substantially less than the 62.5% overhead required by the conventional systems described above, which employ five parity bits for every eight bits of data. Since the overhead is low, error detection and correction can be provided within implantable devices that would not otherwise be able to accommodate conventional error detection and correction systems. Although multiple-bit errors cannot be corrected with this system, the error correction software can typically detect such errors, depending upon their location in memory, such that other appropriate remedial steps can be taken, such as switching to a backup therapy controller. In any case, the provision of single-bit error detection and correction represents a significant improvement over implantable medical devices that perform no error correction whatsoever.
In accordance with a second aspect of the invention, a software-based error detection and correction system is provided for performing error detection and correction of single-bit upset errors within an implantable medical device. The implantable device includes a microcontroller for controlling operations of the device, a memory unit for storing control software and data for use by the microcontroller, and the software-based error detection and correction system. The microcontroller controls operations of the device by identifying a sequence of successive therapy delivery cycles and administers therapy, if necessary, based on the cycles. The error detection and correction system operates between successive cycles to examine portions of memory to identify any single-bit errors therein. If an error is detected, the software-based error detection and correction system corrects the single-bit error before the next pacing cycle.
In an exemplary embodiment of the second aspect of the invention, the implantable device is a cardiac stimulation device for administering pacing therapy. The memory employs eight-bit RAM chips without hardwired parity bits. Each page of memory represents one row of a multi-page memory array. One page parity bit is stored for each page of the memory array. A set of column parity bytes and one array parity bit are stored for the entire memory array. The page, column, and array parity bits are calculated by the software-based error detection and correction system and are stored in memory. The error detection and correction system unit operates between pacing cycles to perform a parity check on each page of data in the array and to correct any single-bit upset errors therein. By providing error detection and correction between pacing cycles, single bit errors can be detected before therapy is administered such that inappropriate therapy is avoided. The total error detection and correction overhead is significantly less than that of the byte-based embodiment summarized above and dramatically less than conventional thirteen-bit systems. Indeed, for a 32 K-byte memory chip with a page size of 128 bytes, the total parity bit overhead is only 0.49%. Moreover, because error detection and correction is implemented with software, implantable devices that have already been implanted can be upgraded to incorporate error detection and correction, so long as sufficient memory space is available for the additional error detection and correction software. As with the byte-based system summarized above, multiple-bit errors typically can be detected but not corrected with this system.
Other objects and advantages of the invention are achieved as well. Method embodiments of the invention are also provided.